Hitachi and Renesas Technology released a 0.05mm x 0.05mm x 5um ultra-small RFID tag (wireless tag) IC (speech number: 26.6) at ISSCC 2007. Compared with the "new generation Î¼ chip" of 0.15mm Ã— 0.15mm Ã— 7.5Î¼m released on the last ISSCC, the size is smaller, only 2/27 of it.
This time, the IC was fabricated using 90nm CMOS technology based on SOI backplanes. It is equipped with three layers of metal wiring and also has a memory with a size of 21 Î¼mÃ—32 Î¼m and a storage capacity of 128 bits. Using an optional external antenna, it can communicate with a wireless tag reader at a frequency of 2.45 GHz. The maximum communication distance is 300mm. The power consumption at the time of communication was "less than 1mW" (presenter: Hitachi, Ltd., Central Research Institute, Research Institute, Masuhiro Sugao).
Similar to the 0.15mm square IC, this time the wireless tag IC has electrodes on both sides of the IC that are connected to the antenna. The reason for this design is that due to the small size of the IC, if the antenna is connected to both sides of the IC, the high cost will be required. By arranging the electrodes on both sides, there is no need to fine-tune the direction and position. The antenna uses the length of the original wireless tag - about 6cm. The bonding of the antenna and the IC employs an "ACF (asymmetric conductive film)".
1 million wafers for 1 wafer
Lithography of memory uses electron beam (EB). The reasons for use are as follows: (1) In the future, it will be easier to manufacture micro-transistors, (2) The memory made of electron beam can ensure high reliability at a high temperature of 400Â°C, (3) Only the unique ID design drawing will be needed. Embedded memory without mask. Although EB equipment is very expensive, "this time, 4 million ICs can be obtained for a single wafer. In this way, the cost of EB is not a problem. It is easier to implement ultra-small IC designs with advanced lithography technology." Hitachi, Ltd. Usami.
The SOI substrate is used in the manufacturing process to increase isolation between the IC and peripheral parasitic capacitance. "If you reduce the size of the IC, parasitic capacitance and other factors around the IC can easily cause the latch-up effect (LATCH-UP), and sometimes it will cause the opposite voltage to be applied to the IC. Previously, the Guard Ring was used. However, there is a problem that it is easy to increase the size of the IC. To reduce the size, the SOI substrate must be used.
12Î¼m square IC is also incorporated into the field of view
Hitachi and Renesas Technology plan to further miniaturize the manufacturing process in the future, from the 65nm transition to 23nm, to create 12Î¼m square IC. "With EB, it is also possible to miniaturize the memory."
In addition to manufacturing technology, the key issue currently facing is the processing capability of computers that handle lithographic graphics. â€œIt takes a long time to integrate information processing of a large number of lithographic patterns. This factor is directly related to the throughput of the manufacturing process.â€
Reprinted from: Nikkei BP Agency Nozawa Tetsuko
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